December 11, 2013
Fraunhofer IISB, Erlangen
Fraunhofer IISB, Erlangen
Specialized processes for MEMS device release and in-situ wafer level encapsulation
David Springer, SPTS Technologies Ltd., Newport, United Kingdom
Fabrication of ultra-thin chips on the basis of porous silicon
Saleh Ferwana, Institut für Mikroelektronik Stuttgart (IMS CHIPS), Stuttgart, Germany
SWAT – A new CU WET etch approach
Stephan Henneck, Infineon Technologies AG, Regensburg, Germany
Electrostatic supported thin-wafer processing in plasma processes by means of the T-ESC® technology
Sebastian Wagner, ProTec Carrier Systems GmbH, Siegen, Germany
Refurbishment of ceramic ESC for etch
Dietmar Hellmann, CE-MAT GmbH, Freigericht, Germany
Profile simulations of plasma etching of silicon
Valentyn Ishchuk, Technische Universität Ilmenau, Ilmenau, Germany
Coupled equipment- and feature-scale simulation of PECVD of SiO2
Eberhard Baer, Fraunhofer IISB, Erlangen, Germany
Measurement of trench geometry and poly recess depth by scatterometry
Franz Heider, Infineon Technologies Austria AG, Villach, Austria
A novel method for nanotopography measurement on Si wafers
Alexander Tobisch, Fraunhofer IISB, Erlangen, Germany