Joining European Forces for Sustainable Power Electronics: Fraunhofer IISB Contributes to FastLane EU

Kurzmeldung /

© Fabio Ribeiro
After one year of intense preparations, the first in-person meeting of the consortium was held at the premises of the coordinator Valeo France in Créteil in June 2024.
© Michael Jank / Fraunhofer IISB
Dr. Michael Jank (left) and Norman Boettcher from the IISB's Advance Research & Development Department took part in the project kick-off for FastLane.

Norman Boettcher and Dr. Michael Jank from the IISB's Advance Research & Development Department had the pleasure to celebrate the project kick-off for FastLane with the entire community, a total of 29 partners along the value chain for silicon carbide (SiC). FastLane sets sail to boost European capabilities in engineered SiC substrates, monolithically and heterogeneously integrated power devices as well as assembly technologies. The aim is a system demonstration for drive train and energy applications.

Fraunhofer IISB offers a complete R&D value chain for SiC spanning all areas of the institute. The institute contributes to FastLane with four departments, specifically Materials, Advance Research & Development, Front End and Vehicle Electronics. Within FASTLANE, the IISB provides expertise in SiC materials characterization, research into SiC epitaxy, and the improvement and system integration of its unique monolithically integrated SiC Solid-State Circuit Breaker.
 

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Flyer: Monolithically Integrated SiC Circuit Breaker

ACKNOWLEDGMENT: The project is supported by the Chips Joint Undertaking (JU) and its members, including top-up funding by Austria, France, Germany, Romania, Slovakia, under grant agreement No 101139788.

Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or Chips Joint Undertaking. Neither the European Union nor the granting authority can be held responsible for them.

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